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HD74SSTV16859
1:2 13-bit SSTL_2 Registered Buffer
REJ03D0832-0900 (Previous: ADE-205-337H) Rev.9.00 Apr 07, 2006
Description
The HD74SSTV16859 is a 1:2 13-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from D to QA, QB is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins. When RESET is low, all registers are reset and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
Features
* * * * Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input ) Differential SSTL_2 (Stub series terminated logic) CLK signal Flow through architecture optimizes PCB layout Ordering Information
Part Name HD74SSTV16859TEL Package Type TSSOP-64 pin Package Code (Previous code) PTSP0064KA-A (TTP-64DV) T Package Abbreviation Taping Abbreviation (Quantity) EL (1,000 pcs / Reel)
Function Table
Inputs RESET L H H CLK CLK LK L X CLK X D X H L QA L H L
*1
Outputs QB L H L Q0
*1
H L or H H or L X Q0 H: High level L: Low level X: Immaterial : Low to high transition : High to low transition Note: 1. Output level before the indicated steady state input conditions were established.
Rev.9.00 Apr 07, 2006 page 1 of 10
HD74SSTV16859
Pin Arrangement
Q12A 1 Q11A 2 Q10A 3 Q09A 4 Q08A 5 VDDQ 6 GND 7 Q07A 8 Q06A 9 Q05A 10 Q04A 11 Q03A 12 Q02A 13 Q01A 14 GND 15 Q00A 16 Q12B 17 VDDQ 18 Q11B 19 Q10B 20 Q09B 21 Q08B 22 Q07B 23 Q06B 24 Q05B 25 GND 26 VDDQ 27 Q04B 28 Q03B 29 Q02B 30 Q01B 31 Q00B 32
64 VDDQ 63 GND 62 D12 61 D11 60 VCC 59 VDDQ 58 GND 57 D10 56 D9 55 D8 54 GND 53 D7 52 D6 51 RESET RESE 50 GND 49 CLK 48 CLK 47 VDDQ 46 VCC 45 VREF 44 D5 43 GND 42 D4 41 D3 40 D2 39 GND 38 VDDQ 37 VCC 36 D1 35 D0 34 GND 33 VDDQ
(Top view)
Rev.9.00 Apr 07, 2006 page 2 of 10
HD74SSTV16859
Absolute Maximum Ratings
Item Supply voltage Input voltage *1 Output voltage *1 Input clamp current Output clamp current Continuous output current VCC, VDDQ or GND current / pin Maximum power dissipation at Ta = 55C (in still air) Storage temperature Notes: Symbol VCC or VDDQ VI VO IIK IOK IO ICC, IDDQ or IGND PT Tstg Ratings -0.5 to 3.6 -0.5 to VDDQ+0.5 -0.5 to VDDQ+0.5 50 50 50 100 1 -65 to +150 Unit V V V mA mA mA mA W C Conditions
VI < 0 or VI > VCC VO < 0 or VO > VDDQ VO = 0 to VDDQ TSSOP
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Recommended Operating Conditions
Item Supply voltage Output supply voltage Reference voltage Termination voltage Input voltage AC high level input voltage AC low level input voltage DC high level input voltage DC low level input voltage High level input voltage Low level input voltage Differential (Common mode range) input voltage (Minimum peak to
peak input)
Symbol VCC VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VCMR VPP IOH IOL Ta
Min VDDQ 2.3 1.15 VREF-40 mV 0 VREF+310 mV -- VREF+150 mV -- 1.7 -0.3 0.97 360 -- -- 0
Typ 2.5 2.5 1.25 VREF -- -- -- -- -- -- -- -- -- -- -- --
Max 2.7 2.7 1.35 VREF+40 mV VCC -- VREF-310 mV -- VREF-150 mV VDDQ+0.3 0.7 1.53 -- -20 20 70
Unit V V V V V V V V V V V V mV mA mA C
Conditions
VREF = 0.5 x VDDQ
D D D D RESET RESET CLK, CLK CLK, CLK
High level output current Low level output current Operating temperature
Note: The RESET input of the device must be held at VDDQ or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is low.
Rev.9.00 Apr 07, 2006 page 3 of 10
HD74SSTV16859
Logic Diagram
*1
RESET CLK CLK D0
51 48 49 35
1D C1
45
16 32
Q00A Q00B
VREF
R
To twelve other channels
Note:
1. RESET input gate is connected to VDDQ.
Electrical Characteristics
Item Input diode voltage Output voltage Symbol VIK VOH VOL Input current (All inputs) Quiescent supply current Standby current Dynamic operating clock only IIN ICC *2 ICC (stdy) ICCD *2 VCC (V) 2.3 Min -- Typ -- -- -- -- -- -- -- -- -- Max -1.2 -- VDDQ 0.2 0.35 5 45 10 90 Unit V V Test Conditions IIN = -18 mA IOH = -100 A IOH = -16 mA IOL = 100 A IOL = 16 mA VIN = 2.7 V or 0 VIN = VIH(AC) or VIL(AC), IO = 0 RESET = GND RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50%
2.3 to 2.7 VCC-0.2 2.3 1.95 2.3 to 2.7 -- 2.3 0 2.7 -- 2.7 -- 2.7 -- 2.7 --
A mA A A/ clock MHz A/ clock MHz/ data input pF
duty cycle Dynamic operating per each data input ICCD
*2
2.7
--
--
20
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle.
Output high *3 Output low *3 rOH - rOL each *3 separate bit Input capacitance Notes: 1. 2. 3. 4. Data inputs
CLK and CLK
rOH rOL rO() CIN
2.3 to 2.7 2.3 to 2.7 2.5 2.5 *1
7 7 -- 2.5 2.5 --
-- -- -- -- -- 3.0
22 *4 22 *4 4 3.5 3.5 --
IOH = -20 mA IOL = 20 mA IO = 20 mA, Ta = 25C VI = VREF310 mV
VCMR = 1.25 V, VPP = 360 mV
RESET
VI = VCC or GND
All typical values are at VCC = 2.5 V, Ta = 25C. Total ICC (max) = ICC + {ICCD (clock)xf(clock)} + {ICCD (Data)x1/2f(clock)x13} This is effective in the case that it did terminate by resistance. See figure. 1, 2
Rev.9.00 Apr 07, 2006 page 4 of 10
HD74SSTV16859
Switching Characteristics
Item Clock frequency *1 Setup time Fast slew rate *4, 6 Slow slew rate *5, 6 Hold time Fast slew rate *4, 6 Slow slew rate *5, 6 Differential inputs active time Differential inputs inactive time Symbol fclock tsu th tact tinact VCC = 2.5 0.2 V Min Max -- 200 0.75 -- 0.9 -- 0.75 -- 0.9 -- 22 -- 22 -- Unit MHz ns ns ns ns Test Condition Data before CLK, CLK Data after CLK, CLK Data inputs must be low after RESET high. Data and clock inputs must be held at valid levels (not floating) after RESET low. CLK, CLK "H" or "L"
Pulse width Output slew *3
tw tSL
2.5 1
-- 4
ns volt/ns
(CL = 30 pF, RL = 50 , VREF = VTT = VDDQ x 0.5)
Item Maximum clock frequency Propagation delay time Notes: 1. 2. 3. 4. 5. 6.
*2
Symbol fmax
VCC = 2.5 0.2 V Min 200 Typ -- Max --
Unit MHz
FROM (Input)
TO (Output)
tPLH, tPHL 1.1 -- 2.8 ns CLK, CLK QA, QB tPHL -- -- 5.0 RESET QA, QB Although the clock is differential, all timing is relative to CLK going high and CLK going low. lative This timing relationship is specified into test load (see waveforms - 3, 4) with all of the outputs switching. Assumes into an equivalent, distributed load to the address net structure defined in the application def information provided in this specification. For data signal input slew rate 1 V/ns. For data signal input slew rate 0.5 V/ns and < 1 V/ns. CLK, CLK signals input slew rates are 1 V/ns.
Rev.9.00 Apr 07, 2006 page 5 of 10
HD74SSTV16859
Test Circuit
VTT
*2
50 Test point
*1
C L = 30 pF
Notes:
1. CL includes probe and jig capacitance. 2. VTT = VREF = VDDQ x 0.5
Waveforms - 1
LVCMOS RESET Input VCC VCC /2 tinact
*1
VCC /2 0V tact 90 % 10 % I CCH I CCL
I CC
Waveforms - 2
tw VIH Input VREF VREF VIL
Timing input
VCMR
VPP
tsu
th VIH
Input
VREF
VREF VIL
Rev.9.00 Apr 07, 2006 page 6 of 10
HD74SSTV16859 Waveforms - 3
Timing input VCMR VCMR VPP
tPLH
tPHL V OH
Output
VTT
VTT VOL
Waveforms - 4
LVCMOS RESET Input VIH VCC /2 VIL tPHL VOH Output VTT VOL
Notes:
1. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. 2. All input pulses are supplied by generators having the following characteristics : PRR 10 MHz, Zo = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). , 3. The outputs are measured one at a time with one transition per measurement. 4. VTT = VREF = VDDQ/2 5. VIH = VREF+310 mV (AC voltage levels) for differential inputs. VIH = VCC for LVCMOS input. 6. VIL = VREF-310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH and tPHL are the same as tpd
Rev.9.00 Apr 07, 2006 page 7 of 10
HD74SSTV16859
Application Data
* Pull-down
100
80
Current (Amps)
60
40
20
Min Max
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Voltage (V)
Figure 1
* Pull-up
Voltage (V)
0.0 0 0.5 1.0 1.5 2.0 2.5 Min Max 3.0
-20
Current (Amps)
-40
-60
-80
-100
Figure 2
Rev.9.00 Apr 07, 2006 page 8 of 10
HD74SSTV16859
Curve Data
Pull-down Voltage (V) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 I (mA) Min 0 6 10 15 19 23 27 30.5 34 36.5 38.5 40 42 43 44 44 45 45 45 45 45 46 46 46 46 46 46 46 I (mA) Max 0 7 15 22 29 35.5 41.5 48 54 59 65 70 75 79 82 84.5 87 89 90 90 91 91 91 91 91.5 92 92 92 I (mA) Min 0 -5 -10 -15 -19 -23.5 -28 -31.5 -35 -38 -41 -44 -46 -48 -50 -51 -52 -52 -52.5 -53 -53 -53.5 -54 -54 -54 -54.5 -55 -55 Pull-up I (mA) Max 0 -7 -13 -19 -25 -31 -37 -42 -47 -53 -58 -62 -66 -71 -74 -77 -81 -84 -86 -89 -91 -92 -93 -94 -95 -96.5 -98 -99
Rev.9.00 Apr 07, 2006 page 9 of 10
HD74SSTV16859
Package Dimensions
JEITA Package Code P-TSSOP64-6.1x17-0.50 RENESAS Code PTSP0064KA-A Previous Code TTP-64DV MASS[Typ.] 0.47g
*1
D F 33
64
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Terminal cross section ( Ni/Pd/Au plating )
*2
1 Z e
*3
32 bp x M
Reference Dimension in Millimeters Symbol
c
Min
L1
y
A1
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Nom Max 17.0 17.2 6.10
0.00 0.05 0.10 1.20 0.15 0.20 0.25 0.10 0.15 0.20 0 8 7.90 8.10 8.30 0.50 0.08 0.08 0.90 0.4 0.5 0.6 1.0
Rev.9.00 Apr 07, 2006 page 10 of 10
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